The structure of a DRAM cell according to a conventional method is illustrated in FIG. 1.
Referring to FIG. 1, a conventional DRAM cell having a stacked capacitor structure is largely comprised of silicon substrate 10, a transfer transistor, a stacked capacitor, and bitline 20. The transfer transistor has a planar structure including gate insulating film 11 formed on substrate 10, gate 12 which is formed on gate insulating film 11 and serves as a wordline, and source/drain regions 13 and 14 formed on both sides of gate 12 in substrate 10. The stacked capacitor has a planar structure including storage node 21 connected to drain region 14 of the transfer transistor through capacitor contact 24, capacitor dielectric film 22 formed on storage node 21, and plate node 23 formed on capacitor dielectric film 22. Bitline 20 is connected to source region 13 of the transfer transistor through bitline contact 15. In FIG. 1, reference numeral 25 represents an interlayer insulating film.
A conventional DRAM cell has a structure in which bitline contact 15 and storage node contact 24 are arranged on silicon substrate 10 in a plane. Therefore, the cell area is wide, which is disadvantageous for higher integration devices.
Further, for isolating devices from each other in the conventional DRAM cell, an isolation film is formed using a local oxidation of silicon (LOCOS) or trench. This causes a problem in that the cell size is influenced by the isolation technique.
Moreover, as illustrated in FIG. 1, in the case where a stacked capacitor is used as the capacitor of the DRAM cell, a problem may result in that increased step differences of the cell are inevitably caused by the steps taken to increase the capacitance.